New Electronic Divices: Electronics Circuit

Electronics Circuit Biography
Signal Integrity Analysis for 3-D Integrated Circuits --
Integrated Systems Lab, EPFL, 2010-2012.
Modeling the combined effect of process variations and power supply noise on 3-D CDNs. A statistical model consisting of skew and jitter is proposed. New topologies of single- and multi-domain 3-D CDNs are proposed. Developing a buffer insertion algorithm for 3-D interconnects.

-- Power Grid Analysis for 3-D ICs --
Intel Braunchsweig Lab, Germany and LSI-EPFL, 2011.10-2012.1.
Developing a fast IR-drop analysis algorithm and tool for 3-D circuits. Collaboration with Intel Braunchsweig Lab, Germany.

-- Modeling Thermal Through Silicon Vias in 3-D ICs --
Integrated Systems Lab, EPFL, 2010.
Two novel thermal resistor networks are proposed to analytically model the steady-state heat transfer through TTSVs. Analyzing the effect of TTSV parameters on the temperature of circuits.

-- SK-M project --
Design of an SoC with 24 main function modules.
Microprocessor R&D Center in Peking University, Beijing, China, 04.2007 – 06.2008.
Project Manager of IC group.
Organized the entire IC implementation of SoC.
Optimized the timing of CPU Floating Point Unit and clock structure of SoC.
Established the Multi-Voltage synthesis flow for CPU.

-- PKUnityX86 project --
Design of an X86 CPU based on Geode GX2 transferred by AMD.
Microprocessor R&D Center in Peking University, Beijing, China, 10.2006 – 01.2007.
Established semi-custom flow for X86 architecture.
Optimized the clock structure.
Evaluated different types of memory used in CPU.

Electronics Circuit